New

Mixed Signal Modeling and Verification Engineer (UL-50024688)

Cirrus Logic
United States, Texas, Austin
800 West 6th Street (Show on map)
Apr 04, 2025
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn't do it without our extraordinary workforce - and that's where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! We are seeking creative and hardworking engineers to join our outstanding Analog/Mixed-Signal Verification team. You will collaborate with systems and design teams to facilitate top down design methodology. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. This position will play a vital role streamlining development methodology for our organization. We are proud of our outstanding environment and multi-faceted culture. Join us and be part of our journey, innovating incredible technology on a global basis! Responsibilities: Collaborate with multi-functional teams to streamline chip-level integration You will contribute to a team that performs verification planning and AMS simulation on full custom ASICs Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types(sv-udt), & Verilog AMS Develop test plans, test benches, and verification methodologies to verify the microarchitecture and design Performing regression debug support and other flow/infrastructure development Independent Interpretation of analog circuit schematics into abstract models Collaborate with system architects and designers to streamline architectural exploration of next-generation IP Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow Required Skills and Qualifications: MS or higher in Electrical Engineering or Computer Engineering and 5+ years of verification experience in mixed-signal products Strong background in analog integrated circuit design Strong background in System Verilog for real number modeling (RNM) modeling, test bench development & verification Solid understanding and hands on experience on the design of mixed signal designs Organized and detailed with strong communication skills Possess outstanding analytical and problem-solving skills Hard-working and ability to operate in dynamic environment Preferred Skills and Qualifications: Python skills would be highly desirable Teaming closely with digital/analog designers, applications engineers, and manufacturing test to support both pre-silicon verification and post-silicon validation efforts Knowledge of signal processing and System Verilog Assertions and PSL Assertions Ability to create, evaluate, debug, and improve a verification process Opportunity to mentor junior engineers in verification methodology UVM experience would be highly desirable Prior experience with SDF annotation in AMS simulations Prior experience with UPF or CPF Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.